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Semiconductor MSM6542-01/02/03
MSM6542-01/02/03 DESCRIPTION
The MSM6542 is a perpetual-calendar-based real time clock with an alarm function which can read and write data in units of seconds. It can be connected to various buses and can function as a peripheral IC of a microcomputer. The clock ranges are seconds, minutes, hours, days, months, years, and days of the week. The alarm ranges are seconds, minutes, hours, days, months, and days of the week. An event trigger is generated when the time matches the specified time and an alarm occurs or when the clock counter generates a carry. The interrupt and pulse outputs are provided for each of an alarm and a carry. An interface with a microcomputer is implemented by four data bus pins, four address bus
Semiconductor
REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT
bus pins, three control bus pins, and two chip select pins. These pins are used to write or read data from the clock, alarm, and control registers, or to modify the data. The MSM6542 has an address latch enable (ALE) input pin, allowing the data bus and address bus to be shared. When the ALE input pin is kept high, the data bus and address bus can be exclusively used. Other functions of the MSM6542 are: a 30second adjustment, stop and restart of clock, data registers as RAM, and data register (RAM) protection. The CMOS circuitry used in the MSM6542 affords low power dissipation. The crystal oscillator operates at 32.768 kHz. Provisions for backup time keeping are included.
FEATURES
* Real time clock providing seconds, minutes, hours, days, months, years, and days of the week. * Multiple alarm ranges covering seconds, minutes, hours, days, months, and days of the week. A desired alarm range can be selected. * A periodic interrupt output interval can be selected over a wide range from 1/1024 seconds up to 10 minutes. * Interface flexibility allows for connection to many types of microprocessors. * Single read-out procedure (Read flag). * Single power sense circuitry. (Data protect function). * Unused registers can be used as RAM. * 30-second adjustment by software or hardware (software only for the MSM65421/-2). * Stop and restart of clock by software or hardware (software only for the MSM65421/-2). 68 * 1 Hz output for adjustment and check of oscillation frequency (MSM6542-3 only). * User selection of 12 or 24 hour clock mode. * Address latch enable (ALE) input pin. * Advanced CMOS circuitry allows low stand-by voltage and current. * User standard 32.768 kHz oscillator crystal * Available in multiple packages 18-pin plastic DIP (for the MSM65421RS/2RS) (DIP18-P-300). 20-pin plastic SOP (for the MSM65421MS-K/2MS-K) (SSOP20-P-250-K). 24-pin plastic DIP (for the MSM65423RS) (DIP24-P-600). 24-pin plastic SOP (for the MSM65423GS-VK) (SOP24-P-430-VK). * Pin assignment compatibility with the MSM6242BRS (The MSM6542-3MSK provides near compatibility.).
Semiconductor PIN CONFIGURATION
MSM6542-01/02/03
MSM6542-01RS 18-pin plastic DIP (top view)
INTERRUPT OUT CS0 ALE A0 A1 A2 A3 RD VSS
MSM6542-02RS 18-pin plastic DIP (top view)
INTERRUPT OUT CS0 ALE A0 A1 A2 A3 E VSS
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
VDO XT XT CS1 D0 D1 D2 D3 WR
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
VDO XT XT CS1 D0 D1 D2 D3 R/W
MSM6542-03RS 24-pin plastic DIP (top view)
PERIODIC OUT CS0 ALARM OUT ALE A0 30Sec. ADJ A1 68/80 A2 A3 (E) RD VSS
MSM6542-01MS-K 20-pin plastic SOP (top view)
24 23 22 21 20 19 18 17 16 15 14 13
1 2 3 4 5 6 7 8 9 10 11 12
VDO XT XT (NC) STOP/START CS1 D0 1Hz D1 D2 D3 WR (R/W) PERIODIC OUT CS0 ALARM OUT ALE A0 30Sec. ADJ A1 68/80 A2 A3 (E) RD VSS
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
INTERRUPT OUT 1 CS0 2 (NC) 3 ALE 4 A0 5 A1 6 A2 7 A3 8 RD 9 VSS 10
20 19 18 17 16 15 14 13 12 11
VDO XT XT (NC) CS1 D0 D1 D2 D3 WR
MSM6542-03GS-VK 24-pin plastic SOP (top view)
MSM6542-02MS-K 20-pin plastic SOP (top view)
INTERRUPT OUT 1 CS0 2 (NC) 3 ALE 4 A0 5 A1 6 A2 7 A3 8 E9 VSS 10
20 19 18 17 16 15 14 13 12 11
VDO XT XT (NC) CS1 D0 D1 D2 D3 R/W
VDO XT XT (NC) STOP/START CS1 D0 1Hz D1 D2 D3 WR (R/W)
NC : NO Connected (open)
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70
RR-S1 R-S10 MI 1 R- RRMI10 R-H1 R-H10 R-W R-D1 R-D10 MO1 MO10 R-Y1 R-Y10 COMPARATOR A L AO RU MT AA-S1 A-S10 MI 1 AAAMI10 A-H1 A-H10 A-W A-D1 A-D10 MO1 MO10 INTERRUPT OUT P E R IO OU DT I C CC' CD' CE' A-EN ABLE CD CE CF
XT
RESET
STOP
32.768KHz
XT
OSC
Less-than-second counter
MSM6542-01/02/03
Control counter
D3 D2
D1 D0
D A T A I. F.
WR or R/W
R/W
RD or E (-1) (-2)
I F
D.P.
A3
FUNCTIONAL BLOCK DIAGRAM (MSM6542-01, 02)
A2
A1
A0
D E C O D E R
R-SI to CF A-SI to CE'
CS0
A D D R E S S I. F.
BANK 1/0
ALE
Semiconductor
CS1
XT
RESET
STOP
1Hz
32.768KHz
Semiconductor
XT
OSC
Less-than-second counter
Control counter
D3 D2
D1 D0 R-S1 R-S10 RMI1 RR- RMI10 R-H1 R-H10 R-W R-D1 R-D10 MO1 MO10 R-Y1 R-Y10
D A T A I. F.
R/W or WR COMPARATOR
R/W A L AO RU MT ALARM OUT
E or RD
68/80
I F
FUNCTIONAL BLOCK DIAGRAM (MSM6542-03)
D.P. A-S1 A-S10 AMI1
A3
AAAMI10 A-H1 A-H10 A-W A-D1 A-D10 MO1 MO10
A2
A1
A0
D E C O D E R
R-SI to CF A-SI to CE'
PERIODIC OUT
CS0 CD CE CF
A D D R E S S I. F. CC'
BANK 1/0 CD' CE' A-EN ABLE
P E R IO OU T D I C
ALE
CS1
30sec. ADJ
MSM6542-01/02/03
STOP/START
71
REGISTER TABLE
72
BANK 0 D0 r-s1 A-S1 A-S10 A-MI1 A-MI10 A-H1 A-H10 A-D1 a-d8 * a-mo8 * * a-e8 - - HD/SFT - CY2 24/12 a-e4 a-w4 a-w2 a-e2 CY1 CAL * * a-mo4 a-mo2 a-mo1 a-mo10 a-w1 a-e1 TEST2 TEST1 CY0 DP * a-d20 a-d10 a-d4 A-D10 A-MO1 A-MO10 A-W A-ENABLE CC' CD' CE' a-d2 a-d1 * a-PM/AM a-h20 a-h10 a-h8 a-h4 r-h2 a-h1 * a-mi40 a-mi20 a-mi10 a-mi8 a-mi4 a-mi2 a-mi1 * a-s40 a-s20 a-s10 r-s10 r-mi1 r-mi10 r-h1 r-h10 r-d1 Real time one-day digit register Real time ten-day digit register Real time one-month digit register Real time ten-month digit register Real time one-year digit register Real time ten-year digit register Real time day-of-week register Control D register r-d10 r-mo1 r-mo10 r-y1 r-y10 r-w1 MASK1 Real time PM/AM ten-hour digit register Real time one-hour digit register Real time ten-minute digit register Real time one-minute digit register Real time ten-second digit register Real time one-second digit register a-s8 a-s4 a-s2 a-s1 Alarm one-second digit register Alarm ten-second digit register Alarm one-minute digit register Alarm ten-minute digit register Alarm one-hour digit register Alarm PM/AM ten-hour digit register Alarm one-day digit register Alarm ten-day digit register Alarm one-month digit register Alarm ten-month digit register Alarm day-of-week register Register to specify the alarm range Control C register Control D' register Control E' register Same as BANK 0 Register name D3 D2 D1 D0 Register symbol Register name BANK 1
A3 A2 A1 A0
A d d r e s s
Register symbol
D3
D2
D1
0
00
0
0
R-S1
r-s8
r-s4
r-s2
1
00
0
1
R-S10
-
r-s40
r-s20
2
00
1
0
R-MI1
r-mi8
r-mi4
r-mi2
MSM6542-01/02/03
3
00
1
1
R-MI10
-
r-mi40
r-mi20
4
01
0
0
R-H1
r-h8
r-h4
r-h2
5
01
0
1
R-H10
-
r-pm/am
r-h20
6
01
1
0
R-D1
r-d8
r-d4
r-d2
7
01
1
1
R-D10
*
*
r-d20
8
10
0
0
R-MO1
r-mo8
r-mo4
r-mo2
9
10
0
1
R-MO10
*
*
*
A
10
1
0
R-Y1
r-y8
r-y4
r-y2
B
10
1
1
R-Y10
r-y80
r-y40
r-y20
C
11
0
0
R-W
-
r-w4
r-w2
D
11
0
1
CD
IT/PLS2
IT/PLS1
MASK2
E
11
1
0
CE
IRQ FLAG0
REST
IRQ FLAG2 IRQ FLAG1 Control E register
F
11
1
1
CF
BANKI/0
STOP
30-s READ FLAG Control F register adjustment
Notes:
1. 2. 3. 4. 5.
Semiconductor
6. 7. 8. 9. 10. 11.
Since positive logic is used, the high level on a data bus corresponds to 1 in a register. When DP = 1, data can be written in the BANK 1/0 and DP bits. Wnen 0 is written in the DP bit, a delay is required until the bit is set at 0. READ FLAG and IRQ.FLAG0 are read-only flags. READ FLAG is cleared after data is read from it. IRQ. FLAG1 is cleared after data is read from it with IT/PLS1 set at 1. When IT/PLS1 is 0, only 0 can be written in IRQ. FLAG1 and it cannot be cleared when it is read. Similarly, IRQ. FLAG2 is cleared after data is read from it with IT/PLS2 set at 1. When IT/PLS2 is 0, only 0 can be written in IRQ. FLAG2 and it cannot be cleared when it is read. For the MSM6542-01/02, HD/SFT is set internally at 0. Data can be written in the CC' register but it is cleared when it is read. Therefore, read data is always 0. When r-pm/am is 1, the time is P.M. When it is 0, the time is A.M. This is also true for a-pm/am. The contents of all registers are unpredictable when power is turned on from 0V to 5V. A hyphen in the table indicates that the bit is not present. When the bit is read, it always provides 0. When a bit marked an asterisk (*) in the table is used as part of a clock register or alarm register, it always provides 0 at read. When the bit is used as part of RAM, however, it can be used for read and write.
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating Power supply voltage Input voltage Output voltage Storage temperature range Symbol VDD VI VO TSTG Condition Ta = 25C Ta = 25C Ta = 25C -
MSM6542-01/02/03
Value -0.3 to 7 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150
Unit V V V C
Operation Range
Rating Power supply voltage Clock power supply voltage Crystal oscillator frequency Operating temperature range Symbol VDD VCLK (xt) TOP Condition - - - - Value 4.5 to 5.5 2.0 to 6 32.768 -40 to +85 Unit V V kHz C
Note: The clock power supply voltage is required to assure operation of the crystal oscillator and clock.
DC Characteristics
Rating High input voltage (1) Low input voltage (1) High input voltage (2) Low input voltage (2) Input leakage (1) Symbol VIH1 VIL1 VIH2 VIL2 ILK1 V1 = VDD/0V Condition
(VDD = 5V 10%, Ta = -40 ~ +85C) Min. Typ. Max. 2.2 - 0.8 VDD - -1 - - - - - - 0.8 - 0.2 VDD 1 V Applicable pin CS0, A0 ~A3, D0 ~ D3 RD (E), WR (R/W), ALE, 30-s ADJ STOP/START CS1, 68/80 CS0, ALE, A0 ~ A3, 68/80, RD (E), WR (R/W), CS1, 30-s ADJ A D0 ~ D3, STOP/START STOP/START V A A D0 ~ D3, 1Hz
INTERRUPT PERIODIC ALARM OUT
Input leakage (2) High input current Low input current High output voltage Low output voltage (1) Low output voltage (2) Leakage current
Current consumption (1) Current consumption (2)
ILK2 IIH IIL VOH VOL1 VOL2 IOFFLK IDD1 IDD2 CI1 CI2
VIH = 0.8 VDD VIL = 0.2 VDD IOH = -400 A IOL = 2.5 mA IOL = 2.5 mA VI = VDD/0V Oscillation at 32.768 kHz VDD = 5V CS1 ~ 0V VDD = 2V ~ Input oscillator Frequency 1 MHz
-10 -100 20 2.4 - - - - - - -
- - - - - - - - - 3 5
10 -20 100 - 0.4 0.4 10 30 5 - -
VDD Input pins other than DO to D3 D0 to D3
Input capacitance (1) Input capacitance (2)
pF
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MSM6542-01/02/03 Switching Characteristics
80-xxx Write mode (ALE is always at VDD.)
Semiconductor
(VDD = 5V 10%, Ta = -40 to +85C (in the 80 mode for the MSM6542-01/03)) Rating CS1 set-up time CS1 hold time Address stable before WRITE Address stabel after WRITE WRITE pulse width Data set-up time Data hold time RD/WR recovery time Symbol tC1S tC1H tAW tWA tWW tDS tDH tRCV Condition - - - - - - - - Min. 1000 1000 20 10 120 100 10 100 Typ. - - - - - - - - Max. - - - - - - - - Unit ns ns ns ns ns ns ns ns
VIH2 CS1 A0 ~ A3 CS0 WR tC1S VIH1 VIL1 tAW VIH1 VIL1 tWW VIL1 tDS D0 ~ D3 (Input) VIH1 VIH1 VIL1 VIL1 VIH1 tDH tWA tRCV
VIH2 tC1H VIH1 VIL1
VIH1
VIHI = 2.2V VIL1 = 0.8V
VIH2 = 4 VDD 5 VIL2 = 1 VDD 5
74
Semiconductor
80-xxx Read mode (ALE is always at VDD.)
MSM6542-01/02/03
(VDD = 5V 10%, Ta = -40 to +85C (in the 80 mode for the MSM6542-01/03)) Rating CS1 set-up time CS1 hold time Address stable before READ Address stable after READ RD to data Data hold RD/WR recovery time Symbol tC1S tC1H tAR tRA tRD tDR tRCV Condition - - - - CL = 150 pF - - Min. 1000 1000 20 20 - 10 100 Typ. - - - - - - - Max. - - - - 120 45 - Unit ns ns ns ns ns ns ns
VIH2 CS1 A0 ~ A3 CS0 tC1S VIH1 VIL1 tAR tRA tC1H
VIH2
RD
VIH1
VIL1 tRD
VIL1
VIH1 tDR
tRCV
VIH1
D0 ~ D3 (Output)
VOH VOH VOL VOL
"Z"
VIH1 = 2.2V VIL1 = 0.8V
VIH2 = 4 VDD 5 VIL2 = 1 VDD 5
VOH = 2.2V VOL = 0.8V
75
MSM6542-01/02/03
80-xxx Write mode (ALE is used.)
Semiconductor
(VDD = 5V 10%, Ta = -40 to +85C (in the 80 mode for the MSM6542-01/03)) Rating CS1 set-up time Address set-up time Address hold time ALE pulse width ALE before WRITE WRITE pulse width ALE after WRITE Data set-up time Data hold time CS1 hold time RD/WR recovery time Symbol tC1S tAS tAH tAW tALW tWW tWAL tDS tDH tC1H tRCV Condition - - - - - - - - - - - Min. 1000 25 25 40 10 120 20 100 10 1000 100 Typ. - - - - - - - - - - - Max. - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns
VIH2 CS1 A0 ~ A3 CS0 tC1S tAS VIH1 VIL1 tAW VIH1 ALE WR VIH1 VIL1 tALW VIH1 VIL1 tDS D0 ~ D3 (Input) VIH1 VIL1 VIH1 = 2.2V VIL1 = 0.8V tWW tAH VIH1 VIL1 tC1H
VIH2
tWAL VIH1 VIL1 tDH VIH1 VIL1 VIH2 = 4 VDD 5 1V VIL2 = 5 DD tRCV VIH1
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Semiconductor
80-xxx Read mode (ALE is used.)
MSM6542-01/02/03
(VDD = 5V 10%, Ta = -40 to +85C (in the 80 mode for the MSM6542-01/03)) Rating CS1 set-up time Address set-up time Address hold time ALE pulse width ALE before READ ALE after READ RD to data Data hold CS1 hold time RD/WR recovery time Symbol tC1S tAS tAH tAW tALR tRAL tRD tDR tC1H tRCV Condition - - - - - - CL = 150 pF - - - Min. 1000 25 25 40 10 20 - 10 1000 100 Typ. - - - - - - - - - - Max. - - - - - - 120 45 - - Unit ns ns ns ns ns ns ns ns ns ns
CS1 A0 ~ A 3 CS0
VIH2 tC1S tAS VIH1 VIL1 tAW VIH1 VIH1
tAH VIH1 VIL1 tRCV VIL1 tALR
tC1H
VIH2
ALE
VIL1 tRAL VIH1 tRD VIL1 VOH VOL VIH1 VIL1 tDR "Z" tRCV VIH1
RD
D0 ~ D 3 (Output) VIH1 = 2.2V VIL1 = 0.8V VIH2 = 4 VDD 5 VIL2 = 1 VDD 5
VOH = 2.2V VOL = 0.8V
77
MSM6542-01/02/03
68-xxx
Semiconductor
(VDD = 5V 10%, Ta = 0C to +70C (in the 86 mode for the MSM6542-02/03)) Rating CS1 set-up time R/W address set-up time E 'H' pulse width R/W address hold time E 'L' pulse width E cycle time Data set-up time WRITE data hold time E to data READ data hold time CS1 hold time Symbol tC1S tRWE tEHW tERW tELW tEC tDS tDHW tRD tDHR tC1H Condition - - - - - - - - CL = 150 pF - - Min. 1000 100 220 20 220 500 180 20 - 10 1000 Typ. - - - - - - - - - - - Max. - - - - - - - - 120 - - Unit ns ns ns ns ns ns ns ns ns ns ns
VIH1 = 2.2V VIL1 = 0.8V WRITE mode CS1 VIH2 tC1S VIL1
VIH2 = 4 VDD 5 VIL2 = 1 VDD 5 VIH2 tC1H VIL1
VOH = 2.2V VOL = 0.8V
R/W
CS0 A0 ~ A3
VIH1 VIL1 tRWE VIH1 tEHW VIH1
VIH1 VIL1 tERW tELW
E
VIL1
VIL1 tDHW VIH1 VIL1 tEC
VIL1
tDS D0 to D3 VIH1 VIL1 Input data
READ mode CS1 VIH2 tC1S tC1H VIH2
R/W
VIH1
VIH1
CS0 A0 ~ A3
VIH1 VIL1 tRWE tEHW VIH1 tRD VIH1
VIH1 VIL1 tERW tELW
E
VIL1
VIL1 tDHR
VIL1
D0 to D3
VOH VOH VOL Output data VOL tEC
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Semiconductor DESCRIPTION OF PINS
D0 to D3 (Data bus pins 0 to 3)
MSM6542-01/02/03
These input pins connected to the data bus of a microcomputer are used for the microcomputer to read and write registers. The interface uses the positive logic. When CS0 is low, CS1 is high, RD is low, and WR is high (for the 68-xxx system, CS0 is low, CS1 is high, R/W is high, and E is high), these data bus pins are in the output mode. In the other cases, they are in the high impedance status. A0 to A3 (Address bus pins 0 to 3) These input pins connected to the address bus of a microcomputer specify a register used by the microcomputer for read or write. The address data specified by these pins is used in conjunction with the input to the ALE pin. ALE (Address Latch Enable) This input pin is for address and CS0. When the ALE pin is high, the address bus data and CS0 are read into the IC. When it is low, the address data and CS0 read at ALE = H are retained in the IC. CS1 functions independently of the ALE pin. When using an MSC-48-, MSC-51-, or 8085-based microcomputer having an ALE output pin, connect this pin to the ALE output pin of the microcomputer. When a four-bit microcomputer shares the four address bus pins, A0 to A3, with another peripheral IC, the ALE pin on this IC can be used to specify it. When the microcomputer has no ALE output pin, connect the ALE input pin on this IC to the VDD. WR [R/W] (WRITE [READ/WRITE]) This input pin is connected to the WR pin for the 80-based CPU or the R/W pin for the 68-based CPU. RD [E] (READ [E]) This input pin is connected to the RD pin for the 80-based CPU or the E pin for the 68-based CPU. CS0, CS1 (Chip select pins 0 and 1) These input pins enable or disable input of ALE, WR (R/W), and RD (E). When CS0 is low and CS1 is high, these inputs are enabled. In the other combinations, the IC unconditionally assumes that ALE is low and WR and RD are high (for the 68-based CPU, E is low). However, CS0 needs to operate in conjunction with ALE and CS1 operates independently of ALE. Connect CS1 to the power supply voltage detection pin. For more information, see the descriptions in "USAGE" and "USE OF CS1."
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MSM6542-01/02/03
PERIODIC OUT (Only for the MSM6542-03)
Semiconductor
This output pin is used for N-channel open drain. It outputs a single pulse or an interrupt request as a trigger each time a carry is generated from the clock counter. Output from this pin is not disabled by CS0 and CS1. ALARM OUT (Only for the MSM6542-03) This output pin is used for N-channel open drain. It outputs a single pulse or an interrupt request each time the contents of the clock counter match the date and time for which an alarm is set. Output from this pin is not disabled by CS0 and CS1. INTERRUPT OUT (Only for the MSM6542-01/02) This output pin is N-channel open drain. It ORs the signals from the PERIODIC OUT and ALARM OUT pins above.
VDD Carry trigger PERIODIC OUT
VDD Date and time matching trigger ALARM OUT
VDD Carry trigger Date and time matching trigger INTERRUPT OUT
80
Semiconductor
XT and XT (X'tal OSC)
MSM6542-01/02/03
These pins are the connecting terminals to connect the capacitors and crystal oscillator at 32.768kHz as shown below.
XT 32.768 kHz C1 VDD or GND
5M TYP.
200K TYP.
C2
XT MSM6542
Example (Equivalent series resistance = 30 k < C1, C2 = 15 to 30 pF)
Note:
Oscillation accuracy and allowable values of the equivalent series resistor for the crystal oscillator depend on the value of the capacitor used for oscillation. For selection of a crystal oscillator and the value of the capacitor needed for it, consult the crystal oscillator manufacturer.
To supply external 32.768 kHz clocks, enter CMOS output or pulled-up TTL output to the XT pin and leave the XT pin open. VDD and VSS These are power supply pins. Connect the VSS pin to ground and supply positive power to the VDD pin. The 1 Hz, 30 sec ADJ, STOP/START, and 68/80 pins described below are used only for the MSM6542-03. 1 Hz This output pin is used to confirm the oscillation frequency. It outputs 1-Hz pluses at a duty cycle of 50%. This pin provides one-second output from the clock counter. Therefore, it is cleared to a low when the REST bit is high or 30-second adjustment is performed. When STOP function is performed, the output stops at whatever level the output is at that instant. This pin provides CMOS output level, regardless of the level of the CS1 pin. If a load is connected to this pin during standby operation, the battery will be quickly dissipated.
81
MSM6542-01/02/03
30-sec ADJ (30-seconds Adjustment)
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When this input pin goes high, 30-second adjustment is performed on the rising edge. When not used, connect to ground. STOP/START This input pin can be used as an integrating clock. When the pin is high, clocking at frequencies lower than 4096 Hz stops. When the pin goes low, clocking is resumed. The HD/SFT bit of the CE' register specifies whether the stop/start function is implemented by hardware or software. When not used, connect to ground. For more information, see the description of "CF register" and "CE' register" in "EXPLANATION OF REGISTERS."
STOP bit of the CF register
HD/SFT bit of the CE' register STOP/START
STOP START Inside of the MSM6542 Equivalent circuit of the STOP/START pin
68/80 This input pin selects which CPU this IC is to be connected. To connect the IC to the 68-based CPU, leave the pin at VDD. To connect the IC to the 80-based CPU, leave the pin at the ground level.
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Semiconductor EXPLANATION OF REGISTERS
MSM6542-01/02/03
Registers R-S1, R-S10, R-MI1, R-MI10, R-H1, R-H10, R-D1, R-D10, R-MO1, R-MO10, R-Y1, R-Y10, R-W a) The letter R followed by a hyphen (-) in these register names indicate a realtime register. S1, S10, MI1, MI10, H1, H10, MO1, MO10, Y1, Y10, and W are abbreviations for Second 1, Second 10, MInute 1, MInute 10, Hour 1, Hour 10, Day 1, Day 10, MOnth 1, MOnth 10, Year 1, Year 10, and Week. The value of each register is weighted in BCD. Positive logic is used. For example, when (r-s8, r-s4, r-s2, r-s1) is (1, 0, 0, 1), it indicates 9 seconds. An asterisk (*) in bank 0 in the realtime register table indicates the bit is automatically set at 0 even though the write data is 1, when the CAL bit of the CE' register is high. When the CAL bit is low, registers R-D1, R-D10, R-MO1, R-MO10, R-Y1, and R-Y10 are used as RAM areas. The bits marked * in these RAM areas can be used for write and read operations. For more information, see the description of "CE' register" in "EXPLANATION OF REGISTERS." d) e) Be sure not to set non-existent data in an non-RAM area, that is, realtime registers. Otherwise, a clock error may occur. r-pm/am, r-h20, and r-h10 In the 12-hour clock mode, the possible hours are from 1 A.M. to 12 A.M. and from 1 P.M. to 12 P.M. When the bit is 1, it indicates P.M. When the bit is 0, it indicates A.M. In the 24hour clock mode, the possible hours are from 0 o'clock to 23 o'clock. During write operation, the r-pm/am bit is ignored in the 24-hour clock mode and the rh20 bit in the 12-hour clock mode. During read operation, the r-pm/am bit is unconditionally set at 0 in the 24-hour clock mode and the r-h20 bit in the 12-hour clock mode. f) R-Y1 and R-Y10 The IC described in this manual operates in Gregorian years. When it operates in Japanese calendar years (Heisei), a leap year is also automatically determined. Leap years are 1992, 1996, 2000, 2004, 2008, and so on.
b) c)
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g) R-W
Semiconductor
The R -W bits counts from 0 to 6. An example of weighting is shown in the following table.
r-w4 0 0 0 0 1 1 1 r-w2 0 0 1 1 0 0 1 r-w1 0 1 0 1 0 1 0 Day of the week Sun Mon Tue Wed Thu Fri Sat
Days are not determined from dates.
CD register (Control D Register) a) MASK1 (D0) This bit controls periodic output for which a carry from the clock counter is used as a trigger. When the bit is 0, output is provided from the INTERRUPT OUT pin for the MSM6542-01/ 02 or the PERIODIC OUT pin for the MSM6542-03. When the bit 1, output is disabled. The relationships between causes of periodic output and the status of the MASK1 bit are shown below. (For the MSM6542-01/02, data resulting from the ORing of periodic output and alarm output is output to the INTERRUPT OUT pin. For convenience, however, alarm output is ignored in the following description.)
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i) In the periodic interrupt mode (when the IT/PLS1, bit is 1)
"1" MASK1 bit "0" "0" "1"
MSM6542-01/02/03
No interrupt occurs because the MASK1 bit is 1. Open Low level Interrupt timing The open status is entered when the IRQ FLAG1 is read. (*1) When the IRQ FLAG1 is read during masking, IRQ FLAG1 is not cleared. (*2)
INTERRUPT OUT (-01, -02) PERIODIC OUT (-03)
*1 *2
When DP = 1, the open state is not entered until a certain period passes after an interrupt is generated. (See the description of the CE register.) However, when DP = 1, if the IRQ FLAG1 bit is read out within 122s after an interrupt is generated, it is cleared after 122s from the generation of the interrupt.
ii)
In the periodic pulse output mode (when the IT/PLS1 bit is 0.)
"1" MASK1 bit "0" "0"
"1" The low level is not output because the MASK1 bit is 1. Open Low level Output timing Automatic restoration
INTERRUPT OUT (-01, -02) PERIODIC OUT (-03)
When 0 is written in the IRQ FLAG1 bit, the open state is entered without having to wait for automatic restration
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b) MASK2 (D1)
Semiconductor
This bit controls the alarm output each time the contents of the clock counter match the date and time for which an alarm is set. When the bit is 0, an alarm is output from the INTERRUPT OUT pin for the MSM6542-01/02 or the ALARM OUT pin for the MSM65423. When the bit is 1, alarm output is disabled. The relationships between causes of alarm output and the status of the MASK2 bit are shown below. (For the MSM6542-01/02, data resulting from the OR-ing of periodic output and alarm output is output to the INTERRUPT OUT pin. For convenience, however, periodic output is ignored in the following description.) i) In the alarm interrupt mode (when the IT/PLS2 bit is 1)
"1" MASK2 bit "0" "0" A match for an alarm is not found because the MASK2 bit is 1. Open Low level Match for an alarm The open status is entered when the IRQ FLAG2 is read. (*1) When the IRQ FLAG2 is read during masking, IRQ FLAG2 is not cleared. (*2) "1"
INTERRUPT OUT (-01, -02) ALARM OUT (-03)
*1 *2
When DP = 1, the open state is not entered until a certain period passes after an interrupt is generated. (See the description of the CE register.) However, when DP = 1, if the IRQ FLAG2 bit is read out within 122s after an interrupt is generated, it is cleared after 122s from the generation of the interrupt.
ii)
In the alarm pulse output mode (when the IT/PLS2 bit is 0)
"1" MASK2 bit "0" "0" The low level is not output because the MASK2 bit is 1. Open Low level Match for an alarm Automatic restoration "1"
INTERRUPT OUT (-01, -02) ALARM OUT (-03)
When the IRQ FLAG2 bit is set at 0, the open state is entered without having to wait for automatic restration
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c) IT/PLS1 (D2) (InTerrupt/PuLSe 1)
MSM6542-01/02/03
This bit determines a mode for periodic output. When the bit is 1, a low-level interrupt request is output from the INTERRUPT OUT pin for the MSM6542-01/02 or from the PERIODIC OUT pin for the MSM6542-3. When the bit is 0, a low-level pulse is output. In this case, the MASK1 bit is 0. The output periods of interrupt output and pulse output are determined by the setting of the CD' register. d) IT/PLS2 (D3) (InTerrupt/PuLSe 2) This bit determines a mode for alarm output. When the bit is 1, a low-level alarm interrupt request is output from the INTERRUPT OUT pin for the MSM6542-01/02 or from the ALARM OUT pin for the MSM6542-03. When the bit is 0, a low-level pulse is output. In this case, the MASK2 bit is 0. When the contents of the alarm register match those of the realtime counter within the range specified by the A-ENABLE register, an output waveform is provided. In the alarm pulse output mode, the low level of a pulse lasts for about 61 s. CE register (Control E register) a) IRQ FLAG1 (D0) (Interrupt ReQuest FLAG1) The status of this bit depends on the hardware output, low or open, from the PERIODIC OUT pin for the MSM6542-3 or INTERRUPT OUT pin which uses carry as a trigger for the MSM6542-1/2. When hardware output is low, the bit is set at 1. When it is open, the bit is set at 0. The IRQ FLAG1 bit is mainly used to indicate that there is an interrupt request for the microcomputer. When the period set by the D2 (CY2), D1 (CY1), and D0 (CY0) bits of the CD' register expires with the D0 (MASK1) bit of the CD register set at 0, output from the INTERRUPT OUT pin changes from open to low. At the same time, the IRQ FLAG1 bit changes from 0 to 1. When the D2 (IT/PLS1) bit of the CD register is 1 (interrupt mode), the IRQ FLAG1 bit remains at 1 (hardware output is low) until the bit is read. When the bit is read, it is cleared. However, when the IRQ FLAG1 bit is read whithin about 122 s of occurrence of an interrupt with the D0 (DP) bit of the CE' register set at 1, the IRQ FLAG1 bit is not cleared immediately. It is cleared about 122 s after the interrupt occurs. When the bit is read at least about 122 s after an interrupt occurs, it is cleared immediately. In the interrupt mode, writing 0 in the IRQ FLAG1 bit does not clear the bit. When another interrupt occurs with the bit set at 1, it is ignored. When the D2 (IT/PLS1) bit of the CD register is 0 (periodic pulse output mode), the IRQ FLAG1 bit remains at 1 (hardware output is low) until 0 is written in the bit or the automatic restoration time determined by the period set by the D2 (CY2), D1 (CY1), and D0 (CY0) bits of the CD' register expires. When the IRQ FLAG1 bit is read in the periodic pulse output mode, it is not cleared.
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i) In the interrupt mode (when the IT/PLS1 bit is 1) (i-1) When DP is 0:
Semiconductor
IRQ FLAG1
"1" "0" Interrupt timing The IRQ FLAG1 bit is read
IRQ FLAG0
"0"
(i-2)
When DP is 1:
122s "1" "0" Interrupt timing The IRQ FLAG1 bit is read 122s
IRQ FLAG1
IRQ FLAG0
"1" "0"
Note:
When the IRQ FLAG1 bit is read within the 122 s interval with the MASK1 bit set at 1, it is not cleared. The IRQ FLAG1 bit is cleared after the 122 s interval ends.
ii)
In the periodic pulse output mode (when the IT/PLS1 bit is 0)
IRQ FLAG2
"1" "0" Output timing Automatic restoration 0 is written in the IRQ FLAG1 bit with DP set at 0
IRQ FLAG0
"0"
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b) IRQ FLAG2 (D1) (Interrupt ReQuest FLAG2)
MSM6542-01/02/03
The status of this bit depends on the hardware output, low or open, from the ALARM OUT pin for the MSM6542-03 or INTERRUPT OUT pin which uses a match with a set alarm time as a trigger for the MSM6542-01/02. When hardware output is low, the bit is set at 1. When it is open, the bit is set at 1. The IRQ FLAG2 bit is mainly used to indicate that there is an alarm timer interrupt for the microcomputer. When the time set by alarm registers, A-S1 to A-W, and the A-ENABLE register expires with the D1 (MASK2) bit of the CD register set at 0, hardware output changes from open to low. At the same time, the IRQ FLAG2 bit changes from 0 to 1. When the D3 (IT/PLS2) bit of the CD register is 1 (alarm interrupt mode), the IRQ FLAG2 bit remains at 1 (hardware output is low) until the bit is read. When the bit is read, it is cleared. However, when the IRQ FLAG2 bit is read within about 122 s of occurrence of an alarm interrupt with the D0 (DP) bit of the CE' register set at 1, the IRQ FLAG2 bit is not cleared immediately. It is cleared about 122 s after the interrupt occurs. When the bit is read at least about 122 s after an interrupt occurs, it is cleared immediately. In the alarm interrupt mode, writing 0 in the IRQ FLAG2 bit does not clear the bit. When another interrupt occurs with the bit set at 1, it is ignored. When the D3 (IT/PLS2) bit of the CD register is 0 (alarm pulse output mode), the IRQ FLAG2 bit remains at 1 (hardware output is low) until 0 is written in the bit or automatic restoration is performed about 61 s later. When the IRQ FLAG2 bit is read in the alarm pulse output mode, it is not cleared. i) In the alarm interrupt mode (when the IT/PLS2 bit is 1) (i-1)
IRQ FLAG2
When DP is 0:
"1" "0" Alarm interrupt timing The IRQ FLAG2 bit is read
IRQ FLAG0
"0"
(i-2)
When DP is 1:
122s "1" "0" Alarm interrupt timing The IRQ FLAG2 bit is read 122s
IRQ FLAG2
IRQ FLAG0
"1" "0"
Note:
When the IRQ FLAG2 bit is read within the 122 s interval with the MASK1 bit set at 1, it is not cleared. The IRQ FLAG2 bit is cleared after the 122 s interval ends. 89
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ii)
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In the alarm pulse output mode (when the IT/PLS2 bit is 0)
61s IRQ FLAG2 "1" "0" Output timing Automatic restoration 0 is written in the IRQ FLAG2 bit with DP set at 0 IRQ FLAG0 "0"
c)
REST (D2) (RESeT) This bit resets the less-than-second counter. While the bit is 1, the counter is being reset. When 0 is written in the bit, reset is canceled. When CS1 goes low, the REST bit is automatically set at 0. When 1 is written in the bit, the TEST1 and TEST2 bits of the CC' register are also set at 0.
d)
IRQ FLAG0 (D3) (Interrupt ReQuest FLAG0) This bit indicates whether the extended time zone for interrupt output is in progress when the DP is 1. The bit is set at 1 when: (1) the D2 (IT/PLS1) bit of the CD register is 1 (periodic interrupt mode) or the D3 (IT/PLS2) bit of the CD registe is 1 (alarm interrupt mode), (2) the D0 (DP) bit of the CE' register is 1 (data protect mode), and (3) 122 s (extended time zone) do not elapse after a periodic interrupt or an alarm interrupt occurs. When 122 s elapse after occurrence of such an interrupt, the bit is automatically set at 0. The bit is not cleared when it is read. Also, data cannot be written in the bit.
CF Register (Control F Register) a) READ FLAG (D0) This bit indicates a one-second carry. It is used to read time data. When the READ FLAG bit is read, it is reset at 0. The status lasts until the less-than-second realtime counter generates a carry to the one-second counter. When a carry to the one-second realtime counter is generated, the READ FLAG bit is set at 1. The status lasts until the bit is read. When a carry to the one-second realtime counter is generated with the READ FLAG bit set at 1, the bit remains unchanged, i.e., at 1. The READ FLAG bit is also set at 1 when 30-s adjustment is performed by software or hardware. The status last until the bit is read. For the usage of the READ FLAG bit, see "Reading registers" in reference flowcharts.
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b) 30-s ADJ (D1) (30-s ADJustment)
MSM6542-01/02/03
When 1 is written in this bit, software makes a 30-s adjustment. For 125 s after this writing, registers R-S1 to R-W (at addresses 0 to C in bank 0 in the register table) cannot be read or written due to limitations to the inside of the IC. When the CAL bit of the CE' register is 0, however, registers R-D1 to R-Y10 (at addresses 6 to B in bank 0) which can be used as RAM are as can be read or written during 30-s adjustment. The bit remains at 1 for up to 250 s after 1 is written in the bit. Then, the bit is automatically reset at 0. Confirm that the bit is automatically reset at 0 before manipulating registers R-S1 to R-Y10 and R-W (when CAL is 0, R-S1 to R-H10 and R-W). The 30-s ADJ bit is also set at 1 when hardware makes a 30-s adjustment. In this case too, confirm that the bit is automatically reset at 0 before manipulating registers R-S1 to R-Y10 and R-W (when CAL is 0, R-S1 to R-H10 and R-W). When the 30-s ADJ bit is set at 1, the D0 (READ FLAG) of the bit CF register is also set at 1. c) STOP (D2) This bit is used for the integrating clock operated by software. When the bit is set at 1, clocking at 4096 Hz and lower stops. When the bit is set at 0, clocking is resumed. For the MSM6542-3, the HD/SFT bit of the CE' register can be used to select hardware or software to implement the stop/restart function. d) BANK 1/0 (D3) When this bit is set at 1, bank 1 is selected. When it is set at 0, bank 0 is selected. The bit can be set even in the data protect mode. Registers A-S1, A-S10, A-MI1, A-MI10, A-H1, A-H10, A-D1, A-D10, A-MO1, A-MO10, A-W a) The letter A followed by a hyphen (-) in these register names indicate an alarm register. S1, S10, MI1, MI10, H1, H10, MO1, MO10, and W are abbreviations or Second1, Second10, MInute1, MInute10, Hour1, Hour10, Day1, Day10, MOnth1, MOnth10, and Week. The value of each register is weighted in BCD. The positive logic is used. For example, when (a-s8, a-s4, a-s2, a-s1) is (1, 0, 0, 1), it indicates 9 seconds. An asterisk (*) in the alarm register table indicates the bit automatically set at 0 even though the write data is 1. This is true when the alarm register is in the alarm setting range set by the A-ENABLE register. The registers outside the alarm setting range set by the A-ENABLE register are used as RAM areas. The bits marked * in these RAM areas can be used for write and read operations. For more information, see the descriptions of "A-ENABLE." d) Be sure not to set non-existing data in alarm registers in the alarm setting range. Otherwise, an alarm may not be generated.
b) c)
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e) a-pm/am, a-h20, and a-h10
Semiconductor
In the 12-hour clock mode, the possible hours are from 1 A.M. to 12 A.M. and from 1 P.M. to 12 P.M. When the bit is 1, it indicates P.M. When the bit is 0, it indicates A.M. In the 24hour clock mode, the possible hours are from 0 o'clock to 23 o'clock. In the 12-hour clock mode, the a-h20 bit is write-enabled. When 1 is written in it, an alarm indicating an impossible time is generated. This is also true for the other registers: when an impossible alarm time is set, no alarm is generated. In the 24-hour clock mode, the a-pm/am bit is read- and write-enabled but its status is assumed to be always the same as that of the r-pm/am bit. f) A-W The A-W bits use the numbers from 0 to 6. Weight these bits in the same way as for R-W. g) The alarm registers are not incremented or decremented
A-ENABLE Register (Alarm ENABLE) This register sets a comparison range for the real time counter and alarm registers. The alarm registers outside the comparison range can be used as four-bit RAM areas. (The bits marked an asterisk (*) in the register table can be used for write and read operations. When DP is 1, however, write operation is not possible.) The following table shows the relationships between the status of the A-ENABLE register bits and alarm comparison ranges.
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ae8 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ae4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ae2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ae1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Alarm comparlson range None A ~ S1 A-S1 ~ A-S10 A-S1 ~ A-MI1 A-S1 ~ A-MI10 A-S1 ~ A-H1 A-S1 ~ A-H10 A-S1 ~ A-D1 A-S1 ~ A-D10 A-S1 ~ A-MO1 A-S1 ~ A-MO10 A-S1 ~ A-H10, A-W A-S1 ~ A-D1, A-W A-S1 ~ A-D10, A-W A-S1 ~ A-MO1, A-W A-S1 ~ A-MO10, A-W
CC' Register (Control C' Register) This register is a test register. The user can use it when both the TEST1 (D0) and TEST2 (D1) bits of the register are 0. When either or both TEST bits are 1, Oki's test functions are enabled, making the execution results of user's functions unpredictable. When the register is read, it is automatically cleared. The read value is always 0. When 1 is written in the REST (D2) bit of the CE register, the CC' register is automatically set at 0. CD' Register (Control D' Register) This register sets an interrupt period when the IT/PLS1 (D2) bit of the CD register is 1 and a pulse output period when the bit is 0. The following table shows the relationships between the status of the CD' register bits and the length of periods.
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CY2 0 0 0 0 1 1 1 1
CY1 0 0 1 1 0 0 1 1
CY0 0 1 0 1 0 1 0 1
Period 1/1024 s 1/128 s 1/64 s 1/16 s 1/2 s 1s 1 min 10 min
Duty cycle of the low level when IT/PLS1 = 0 1/2 1/2 1/2 1/2 1/2 1/8192 1/491520 1/4915200
CE' Register (Control E' Register) a) DP (D0) (Data Protect bit) This bit has the following two functions: i) ii) Restricts write operation to the IC. Prolongs the resetting of the IRQ FLAG1 bit when the bit is read within 122 s of occurrence of a periodic alarm in the periodic interrupt mode. Also prolongs the resetting the IRQ FLAG2 bit in the same way in the alarm interrupt mode.
i)
Restriction of write operation When the DP bit is 0, normal write operation is enabled. When the bit is 1, however, the IC is write-protected except the BANK 1/0 (D3) bit of the CF register for which write operation is always allowed. The DP bit is designed to protect the registers from extenal noise, particularly erroneous write signal noise which is generated when the standby power supply voltage is switched to the system power supply voltage or vice versa. After the necessary data is written, it is recommended that the DP bit be set at 1 if only read operation is performed.
ii)
Prolongation of reset of the IRQ FLAG bits When the IT/PLS1 (D2) bit of the CD register is 1 (periodic interrupt mode) with the DP bit set at 0, reading the CE register clears the IRQ FLAG1 bit. This is also true for the IT/PLS2 (D3) bit when it is 1 (alarm interrupt mode): reading CE register clears the IRQ FLAG2 bit. When the IRQ FLAG1 bit is read within about 122 s of occurrence of an interrupt with the IT/PLS1 (D2) bit of the CD register set at 1 (periodic interrupt mode), the IRQ FLAG1 bit is not cleared immediately. Similarly, the IRQ FLAG2 bit is not cleared immediately when the IT/PLS2 (D3) bit is 1 (alarm interrupt mode). These IRQ FLAG bits are cleared about 122 s after an interrupt occurs. When these bits are read at least about 122 s after an interrupt occurs, they are cleared immediately. For more information, see the description of "CE REGISTER."
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When an IRQ FLAG bits are read mistakenly due to external noise, particularly erroneous read signal noise which is generated when the standby power supply voltage is switched to the system power supply voltage or vice versa, therefore, the IRQ FLAG bits are not cleared immediately but read at the correct times. When 1 is written in the DP bit, the bit is immediately set at 1 except the following two cases. (i) (ii) The CS1 bit is low. For 62 s immediately after the DP bit changes from 1 to 0.
Writing 0 in the DP bit, that is, canceling data protection is allowed only when: (i) (ii) Zero is written in the DP bit more than 2 ms after CS1 changes from low to high. The CS1 bit is high 11 ms after 0 is written in the DP bit.
Data protection can be canceled because CS1 is high CS1 62s
11ms DPbit 1 is written in the DPbit 0 is written in the DPbit
1 written in the DPbit in this period is ignored
b) CAL (D1) (CALendar) This bit specifies a range in which the realtime counter is incremented. When the bit is 1, the R-S1 to R-Y10 and R-W register can be incremented. When the bit is 0, the R-S1 to R-H10 and R-W registers can be incremented. With the CAL bit set at 1, R-D1 to R-Y10 are used as realtime registers. Therefore, setting an impossible time in these registers causes an error. For the bits marked an asterisk (*) of the R-D10 and R-MO10 registers in the register table, when 1 is written, 0 is automatically set. The alarm comparison range is specified by the A-ENABLE register. When the CAL bit is 0, the R-D1 to R-Y10 registers are not incremented. They can be used as static RAM, enabling arbitrary values to be set. The bits marked an asterisk (*) of the R-D10 and R-MO10 registers in the register table can be subject to both write and read operations. The alarm comparison range is specified by the A-ENABLE register. However, the R-D1 to R-Y10 registers are assumed to always provide a match. When these registers are used as static RAM, they cannot be rewritten when the DP bit is 1.
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c) 24/12 (D2) (24-hour clock/12-hour clock)
Semiconductor
This bit selects a 24-hour clock or 12-hour clock mode. When the bit is 1, the 24-hour clock mode without PM/AM specification is enabled. When the bit is 0, the 12-hour clock mode with PM or AM specified is enabled. When the 24/12 bit is rewritten, data in the R-H1 register and higher will be destroyed. The data needs to be written again. d) HD/SFT (D3) (HarDware/SoFTware)(This bit applicable only to the MSM6542-03) This bit determines which mode, hardware or software, is enabled to validate the stop/start function. When the bit is 1, hardware enables the stop/start function (pin 20). When the bit is 0, software enables the stop/start function (D2 of the CF register) The stop/start function by hardware and that by software cannot be used at the same time. For the MSM6542-01/02, the stop/start function by software is always enabled due to an internal setting on the IC. However, the HD/SFT bit can be read or written to freely regardless of this setting, enabling the bit to be used as a memo bit.
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Pattern layout
MSM6542-01/02/03
The oscillation stage of the 32.768 kHz oscillator circuit is at a high impedance to achieve very low power dissipation. In addition, since sine waves are produced at as low as 32.768 kHz, oscillation waves stay near the threshold for a longer time. For this reason, countermeasures must be taken against power supply noise and external noise from the viewpoint of an analog IC. Countermeasures against power supply noise Insert a 4.7 F tantalum capacitor and 0.01 F ceramic capacitor as close to the IC as possible. When another IC (for example, backup RAM) is used in the battery-backed circuit, also insert a by pass capacitor in that IC. Countermeasures against external noise Place the crystal for the oscillator circuit and the capacitors as close to the IC as possible. Do not route other signal lines in the oscillator circuit regardless of whether the oscillator circuit is placed on the front or back of the PC board. Sufficiently separate the XT and XT signal lines from the other signal lines regardless of whether these signal lines are running on the fron or back of the PC board (see a.. and b.. of the figure below).
a
b
a
b
2
1
1 2
7.5 mm 5 mm
2
1
1 2
0.3 INCH 0.2 INCH
Pass capacitor
VDD XT XT
VDD XT XT NC Enclose the VDD line oscillation section
From VSS pin
From pin 12 (VSS)
a
Bypass b capacitor
a
Bypass capacitor
b
2
1
2
1
VDD XT XT
VDD XT XT NC From pin 12 (VSS)
From VSS pin
For the MSM6542-01/02
For the MSM6542-03 97
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Sample connection to a microcomputer
Semiconductor
Various microcomputers are upgraded day by day. Updated versions of this data sheet may not be capable of keeping pace with this progress. Check the matching of switching characteristics in advance. [For the Z80]
D3 D2 D1 D0 A3 A2 A1 A0
D3 D2 D1 D0 A3 A2 A1 A0
Note: Select either IORQ or MREQ so that the Z80 switching characteristics determined by the crystal oscillator for the Z80 match those of the IC described in this data sheet.
A4 ~ A15 IORQ or MREQ RD WR
Decoder
VDD
CS0 ALE
G1 G2
RD WR
[MCS51]
MSC51 3 PORT 2 1 0 MSM6542 D3 D2 D1 D0 A3 A2 A1 A0
[MC6809]
MC6809 D3 D2 D1 D0 A3 A2 A1 A0 MSM6542 D3 D2 D1 D0 A3 A2 A1 A0
A4 ~ A15
Decoder
CS0
PORT 4~7 ALE RD WR
Decoder
CS0 ALE RD WR
R/W E
VDD ALE R/W E
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Sample peripheral circuits
MSM6542-01/02/03
Before using sample peripheral circuits shown below, check them against the user's system. Power supply circuit (Place a bypass capacitor as close to the IC as possible.) [When power is supplied from the +5V power supply]
+5.1V
A495
VCE (sat) = 0.1V R*
4.7F Tantalum capacitor
51K
10K C372
22 +
+ + 0.01
Ceramic capacitor
V DD MSM6542 VSS
10K
1.2 x 3 = 3.6V Cadmium battery
When the power supply is turned off, inverse current flows temporarily from the collector of the A495 transistor to the emitter. To deal with this problem, use a large value capacitance. R*: For less than charge current limit
IS1588 +5.7V R Alternative circuit C372
V F = 0.69V 4.7 + 0.01
Tantalum Ceramic capacitor capacitor
VDD MSM6542 GND
VF = 0.69V or Schottky diode
Lithium battery R: Limit resistance to conform to the UL standard. The value depends on the nominal capacity of the battery used. Consult the battery manufacture.
Sample main power supply monitor circuit
Main power supply (5V)
One-chip voltage detector IC
Main power supply (5V)
VDD VDD CS1 CS1 VSS This circuit detects a rough voltage level. It is suitable for a system for which the DP bit is set at 1. MSM6542 VSS MSM6542
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Oscillation frequency adjustment [For the MSM6542-01/02]
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Screwdriver used for adjustment 18 VDD 17 XT 16 XT
INTERRUPT OUT VDD 3.3 ~ 10K Frequency counter Eye 1 2 3
Turn on power * X for (D3, D2, D1, D0) is a Don't Care bit CF (1, 0, 0, 0) Read C C' register Banks are switched Dummy read to clear the test bits
CE' (X, X, X, 0) *1 Read CE' register
Procedure for canceling data protection
DP = 0 ? Y
N
CD' (0, CY2, CY1, CY0)
Set a frequency of the signal to be output from pin 1. Examples 64 Hz: (0 0 1 0) (duty cycle: 1/2) 1 Hz: (0 1 0 1) (duty cycle: 1/8192)
CF (0, 0, 0, 0) CE (0, 0, 0, 0) CD (0, 1, 1, 0) Read CE register
Banks are switched. The stop bit is cleared.
The reset bit is cleared Preparation for a carry (oscillation). When an alarm occurs, a carry is inhibited. Dummy read to clear the IRQ FLAG 1 bit
*2
To the next page
100
Semiconductor
MSM6542-01/02/03
Read CE register *3 IRQ FLAG 1 = 1 ? Y CD (0, 0, 1, 0) N A carry (oscillation) is checked
Output of a signal at the frequency set by CD' is command through pin 1.
Frequency adjustment
Frequency counter
Eye
*1 To cancel data protection, oscillation must be in progress. It takes about 13 ms (2 ms during which the writing of DP0 is inhibit in the rising of CS1 plus 11 ms required until DP = 0 is executed.) This loop includes a wait time before oscillation starts. Usually, the loop takes 0.5 to 2 seconds. When the power is turned on, the value of the DP bit is unpredictable. When the value is 0 incidentally, the loop does not return. *2, 3 The IRQ FLAG1 is cleared at the step marked *2. If IRQ FLAG1 = 1 is detected in the loop marked *3, therefore, it means that original oscillation is divided.
Other notes Possible causes why the loop marked *1 or *3 becomes endless Yes * * Oscillation waveform at XT No * * * Incorrect programming The frequency counter is not adjusted. Observe the waveform at pin 1 on an oscilloscope. Oscillation is impeded by a leak due to a dirty PC board. Clean the PC board. The capacitance of the capacitor for oscillation is inadequate. Consult the crystal manufacturer. Defective crystal oscillator or IC. Replace it.
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MSM6542-01/02/03
Semiconductor
Possible causes when the loop marked *1 or *3 takes a long time (2 or 3 seconds or more) * Oscillation is impeded by a leak due to a dirty PC board. Clean the PC board. * The capacitance of the capacitor for oscillation is inadequate. Consult the crystal manufactuer. Possible causes why the frequency counter is not stable. * The frequency counter is not adjusted. Observe the waveform at pin 1 on an oscilloscope. * The pattern layout is incorrect. See the description of "Pattern layout." Insert a bypass capacitor having a capacitance of at least 1 F between the VDD and VSS pins.
102
Semiconductor
For the MSM6542-03
MSM6542-01/02/03
Screwdriver used for adjustment
Frequency counter 24 VDD 23 XT 22 XT 21 17 1Hz
Eye
1
2
3
Turn on power CF (1, 0, 0, 0) Read CC' register
Banks are switched Dummy read to clear the test bits
CE' (X, X, X, 0) *1 Read CE' register N
Procedure for canceling data protection
DP =0? Y CF (0, 0, 0, 0) CE (0, 0, 0, 0) *2 Read CF register
Banks are switched. the stop bit is cleared The reset bit is cleared Dummy read to clear the IRQ FLAG bits
Read CF register *3 READ FLAG=1? Y Frequency adjustment (1Hz) Frequency counter N
For the notes for "1, "2 and "3 and other notes are same as for the MSM6542-01/02.
Eye
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MSM6542-01/02/03
Use of CS1 VIH and VIL of CS1 has the following three functions: 1. 2. 3.
Semiconductor
Validate the interface with the microcomputer when 5V power is used. Inhibit use of the control bus, data bus, and address bus and prevent through-current specific to CMOS input in the standby mode. Protect register data of the IC when the standby mode is entered or exited.
To implement these functions: 1. 2. 3. To validate the interface with the microcomputer when 5V power is used, input must be at least 4/5 VDD. When the mode is switched to the standby mode, input must be 1/5 VDD or less to inhibit use of the buses. In the standby mode, input must be nearly 0V to prevent through-current. When the standby mode is entered or exited, the main power and CS1 must conform the following timing charts:
Note: In the standby mode, the operating power supply voltage is from 4V to 2V (minimum value). Clocking is performed but the interface to the outside of the IC is not assured. When a system is implemented with DP = 0:
Switching to the standby mode 4 ~ 6V Main power supply (5V) 4 ~ 4.5V* POWER OFF 1s(MIN) 1 5 VDD (VDD for the IC described in this data sheet is 2 to 6 V.) 0V
Exiting from the standby mode 4 ~ 4.5V* 1s(MIN) 4 5 VDD
CS1
During the period, CS0 of the IC is high or WR is not generated.
On and after this period, the interface through the IC is possible
The purpose is to maintain data in static RAM in the standby mode. 4 to 4.5V* are measures of the minimum 5-V main power supply voltage at which the CPU does not assure correct program operations. This is also the for the following timing chart:
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Semiconductor
When a system is implemented with DP = 1:
MSM6542-01/02/03
Switching to the standby mode 4 ~ 6V Main power supply (4 ~ 4.5V) CS1 a 2 V or more *1 1 5 VDD
Existing from the standby mode 2 V or more POWER OFF 4 5 VDD b 4 ~ 4.5V *2
0V
*1, *2:
* *
The duration in this interval must be 8.7 ms or less. Through current at the input stage (A0 ~ A3, D0 ~ D3, control inputs) caused by intermediate voltage input level and bus charge current cuaused by not programmed read out operation of CPU will dissipate power source. Therefore, it is recommended that the voltage for monitoring the power supply of the CS1 control system be higher than the main power supply/battery switching voltage so that battery backup is enabled only in the interval from a .. to b .. .
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MSM6542-01/02/03
Reference flowcharts
Semiconductor
In the following flowcharts, description of bank switching is omitted. [Power on sequence when DP is 0]
Apply 5V
(CS1
)
*1 The test bit is cleared. *2 Time until the DP bit becomes 0 under assumption that oscillation is in progress. *3 When the voltage before 5V is applied is 0V, this loop takes the time equal to the one required to start oscillation. Usually, it takes 0.5 to 2 s.
Read C C' register
*1 *3
Read CE' register N CE' register DP 0 Idling for at least 11ms *2
DP = 0 Y
*4 The contents of R-S, to R-Y10 and R-W must be possible values and the values of the other registers must be as expected. *5 Wait time until a carry which may be generated is completed.
Standby
What status before 5V is applied? VDD = 0V No
Unclear
CE register REST 1 No
Are contents of individual register correct Yes Does operator determine that the current time is correct Yes
*5 Check contents of individual register *4
Idling for 123 s
Set individual registers
CE register REST 0
106
Semiconductor
[Power on sequence when DP is 1]
MSM6542-01/02/03
Apply 5V
(CS1
)
*1 The test bit is cleared.
Read CC' register *1
Read C E' register N DP = 1 ? Y CE' register DP 1
CE' register DP 0 Idling for at least 11ms *3 Read CE' register DP = 0 ? Y CE' register DP 1 Standby What status before 5V is applied? VDD = 0V CE' register DP 1 Check contents of individual registers *4 *3 No Unclear No *4 Are connents of individual register correct? Yes Does operator determine that the current time is is correct? Yes *5 N
*2 It takes 9 to 11 ms from when 0 is written in the DP bit to when it is set at 0 in the IC. If 0 is written unintentionally in the DP bit during application of 5V power, it may be set at 0. To prevent this, first set the DP bit at 0 then at 1. When the voltage before 5V is applied is 0V, this loop takes the time equal to the one required to start oscillation. Usually, it takes 0.5 to 2 s. *3 Time until the DP bit becomes 0 under assumption that oscillation is in progress. *4 The contents of R-S1, to RY10 and R-W must be possible values and the values of the other registers must be as expected. *5 Wait time until a carry, which may be generated, is completed.
Idling fore at least 11ms Check that DP is 0 CE register REST 1 Idling for 125 s Set individual registers
CE register REST 0 CE' register DP 1 Check that DP is 1
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MSM6542-01/02/03
Semiconductor
[Temporarily canceling DP = 1 in a system for which DP is set at 1]
DP
0 *1
*1
Idling for at least 11ms Read CE' register Check that DP is 0
Time until the DP bit becomes 0 under assumption that oscillation is in progress. See "Rewriting individual register." Writing 1 in it is inhibited for 62 s after the DP bit is set at 0. This idling is provided to make the DP bit wait to be set at 1.
*2 *3
Rewrite individual registers
*2
Idling DP 1
*3
OR DP 0 *1 Idling Read CE' register N
DP = 0? Y
*1
Processing by other IC or wait time to prevent unnecessary readouts which occur frequently. A measure is 1 ms. See "Rewriting individual register." Wait time to prevent unnecessary readouts which occur frequently. A measrue is 10 s.
Rewrite individual registers
*2
*2 *3
DP
1 *3 N
Idling
DP = 1 Y
108
Semiconductor
[Rewriting individual registers]
MSM6542-010/2/03
When bits other than the BANK 1/0 and DP bits are rewritten, the DP bit must be 0. (a) R-S1 to R-Y10 and R-W (For the MSM6542-3, 30s adjustment must not be performed through pin 6 during rewriting.)
Read CF register
*1
*1
Dummy read to clear the READ FLAG (RF) bit. Processing by other IC or wait time to prevent unnecessary readouts which occur frequently. A measure is 50 ms. To assure that rewriting is completed before the next carry is generated, the time required for the step marked *5 must not be longer than 1 s minus time required for steps marked *2 to *4. Time required for a carry pulse to complete operation
Idling Read CF register *4 RF = 1 ? Y Idling for 65 s
*2 *3 N A carry is found *6
*2
*3, *4, *5
*5
Rewrite R-S1 to R-Y10 and R-W
*6
OR
CE register REST 1 Alternatively, CF register STOP 1 Idling for 126 s *2 Rewrite R-S1 to R-Y10 and R-W *1
*1
Wait time until a carry which may be generated before 1 is written in the REST (or STOP) bit is completed When 1 is written in the REST bit, clocking is delayed for the duration during which the less-thansecond counter is cleared and clocking is stopped until 0 is written in the REST bit. When 1 is written in the STOP bit, clocking is delayed for the duration during which clocking is stopped initial 0 is written in the STOP bit.
*2
REST 0 Alternatively, STOP 1
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MSM6542-01/02/03
(b) * * * * * R-D1 to R-Y10 when the CAL bit is 0 CD, REST bit of CE, and CF (excluding the BANK 1/0 bit) A-S1 to A-M10 and A-W A-ENABLE and CD' CE' (excluding the DP bit) There is no restriction other than by the DP bit.
Semiconductor
(c) BANK 1/0 This bit can be rewritten freely even when the DP bit is 1. (d) 30-s ADJ Method 1
CF register 30-s ADJ 1
Idling
*
*At least about 100 s
Read CF register
Is 30-s ADJ bit 0 ? Y
N
Method 2
CF register 30-s ADJ 1
* Maximum time required for 30sec adjustment under assumption that oscillation is in progress
*
Idling for 255 s
(e) DP DP 1: Rewriting is possible 62 s after the DP bit changes to 0. DP 0: See "Temporarily canceling DP = 1 is a system for which DP is set at 1."
110
Semiconductor
[Reading individual registers] (a) Ordingary registers
MSM6542-010/2/03
Any registers can be read freely. However, the contents of the following bits change after they are read. * CE register IRQ FLAG1 : When 1 is read from this bit with IT/PLS1 set at 1, the bit is cleared after read. For the timing when the bit is cleared, see the description of the IRQ FLAG1 bit of the CE register. When 1 is read from this bit with IT/PLS2 set at 1, the bit is cleared after read. For the timing when the bit is cleared, see the description of the IRQ FLAG2 bit of the CE register. When 1 is read from this bit, the bit is cleared after read. These bits are reset immediately when they are read. Therefore, 0 is always read from these bits.
IRQ FLAG2
:
READ FLAG TEST1, TEST2 (b) Reding time
: :
Method 1 (unscheduled reading)
Read CF register
*1
*1 *2
Dummy read to clear the READ FLAG (RF) bit Time required to increment the ripple counter Loop to retry read because of a carry generated in the one-second digit counter during clock register reading
Idling for 3 s
*2
*3
Read clock registers *3
Read CF register
RF = 0 Y
N There is no carry while the clock registers are being read.
111
MSM6542-01/02/03
Method 2 (periodic readout)
Semiconductor
*1 *2
CD' (0, d2, d1, d0) *2
Only for initial setting at power on The values of d2, d1, and d0 depend on the required minimum time unit as follows: d2 d1 d0
*1
IT/PLS1 MASK1
1 0
When up to 1 s is required When up to 1 min is required
1 1 1
0 1 1
1 0 1
Read CE register Idling
*3 *4
When up to 10 min are required *3 *4
Dummy read to clear the IRQ FLAG1 bit 122 s when the DP bit is 1,0 s when the DP bit is 0
The CPU detects an interrupt Interrupt handling routine Read CE register N
IRQ FLAG1 = 1 Y When DP is 1 *8 Inhibit CPU from accepting interrupts Idling for at least 3 s *7 Read clock registers
*5
When DP is 0
Time required to increment the ripple counter
Idling for at least 3 s
*5
*5
*6, *7 The length of the time must be 122 s or more because interrupt output is delayed 122 s due to DP = 1. The idling market *6 is provided for this adjustment. *8 To assure that readout is completed before the next carry is generated, the time required for these steps must not be longer than the minimum set time unit.
Read clock registers
Idling Allow CPU to accept interrupts
*6
Other causes
112
Semiconductor
Method 3 (for each second carry)
MSM6542-010/2/03
(a) Setting (d2, d1, d0) at (1, 0, 1) in method 2 (periodical readout) described above (b) Polling
Read CF register
*1
Processing by other IC or wait time to prevent unnecessary readouts which occur frequently. A measure is 50 ms. Time required to increment the ripple counter Loop to retry read because of a carry generated during clock register reading
RF = 1 ? Y
N *1 Idling
*2 *3
Idling for 3 s
*2
Read clock registers
Read CF register
RF = 0 ? Y
N *3 Discard read data
Use read data
113
MSM6542-01/02/03
[Setting for periodic pulse output]
Semiconductor
Perform the following setting with the DP bit set at 0. The set values are independent of the setting of the DP bit. (a) Periodic pulse output (*1)
CD register IT/PLS1 0 1 MASK1 CE register IRQ 0 FLAG1 Set CD' register (*, CY2, CY1 CY0) CD register 0 IT/PLS1 0 MASK1
*1
*2
From the viewpoint of software, the IRQ FLAG1 bit is used. From the viewpoint of hardware, pin 1 (PERIODIC OUT) is used for the MSM6542-3 or pin 1 (INTERRUP OUT) for the MSM6542-1/2. For the MSM6542-1/2, a signal resulting from the ORing with output triggered by an alarm is output to pin 1. When alarm factors are not required, the MASK2 bit must be set at 1. The IRQ FLAG1 bit is cleared.
*3
*2
*3
(b) Alarm pulse output (*1)
CD register 0 IT/PLS1 1 MASK1 Idling for 185 s CE register IRQ 0 FLAG
*2
*1
*3
From the viewpoint of software, the IRQ FLAG2 bit is used. From the viewpoint of hardware, pin 2 (ALARM OUT) is used for the MSM6542-3 or pin 1 (INTERRUPT OUT) for the MSM6542-1/2. For the MSM6542-1/2, a signal resulting from the ORing with output triggered by a periodic carry is output to pin 1. When periodic factors are not required, 1 must be set in the MASK1 bit. Time required to delete the previous output factors in the IC. The IRQ FLAG2 bit is cleared.
*2
*4
Set A-ENABLE register (ae8, ae4, ae2, ae1)
*3
Set A-S1 to A-M10 and A-W
*4
CD register 0 IT/PLS2 0 MASK2
114
Semiconductor
[Setting interrupt conditions]
MSM6542-010/2/03
Perfomr the following setting with the DP bit set at 0. The set values are independent of the setting of the DP bit. (a) Periodic interrupt output (*1)
*1
CD register IT/PLS1 1 * 2 1 MASK1 Dummy readout of CE register Set CD' register (*, CY2, CY1, CY0) CD register IT/PLS1 1 0 MASK1 *3
From the viewpoint of software, the IRQ FLAG1 bit is used. From the viewpoint of hardware, pin 1 (PERIODIC OUT) is used for the MSM654203 or pin 1 (INTERRUPT OUT) for the MSM654201/02. For the MSM6542-1/2, a signal resulting from the ORing with output triggered by an alarm is output to pin 1. When alarm factors are not required, the MASK2 bit must be set at 1. The IRQ FLAG1 bit is cleared.
*2
*3
(b) Alarm interrup output (*1)
CD register 1 IT/PLS2 MASK2 1 Idling for 185 s
*2
*1
*3 *4
From the viewpoint of software, the IRQ FLAG2 bit is used. From the viewpoint of hardware, pin 3 (ALARM OUT) is used for the MSM6542-03 or pin 1 (INTERRUPT OUT) for the MSM654201/02. For the MSM6542-01/02, a signal resulting from the ORing with output triggered by a periodic carry is output to pin 1. When periodic factors are not required, 1 must be set in the MASK1 bit. Time required to output the previous interrupt factors The IRQ FLAG2 bit is cleared.
Dummy readout of CE register
*2
Set A-ENABLE register
Set A-S1 to A-M1O and A-W
*3
CD register 1 IT/PLS2 0 MASK2
*4
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MSM6542-01/02/03
[Sensing interrupts] (a) When the DP bit is 0
Interrupt
Semiconductor
Read CE register
Are both IRQ FLAG1 and IRQ FLAG2 bits 0? N
Y
Another IC is an interrupt factor
Take action for IRQ FLAG1 and IRQ FLAG2
(b) When the DP bit is 1
Interrupt
*1
Read CE register
Are both IRQ FLAG1 and IRQ FLAG2 bits 0? N ID on CPU side *1
Y Another IC is an interrupt factor
ID: Interrupt Disable Take action for IRQ FLAG1 and IRQ FLAG2 Read CE register
When the IRQ FLAG1 and IRQ FLAG2 bits are read, they are cleared. Restoration of these pins to the open output status is delayed up to 122 s. For this reason, the CPU is interruptdisabled --- the CPU cannot accept interrupts. When the maximum delay of 122 s described in *1 elapses, the IRA FLAG0 bit is set at 0. Since hardware output requesting an interrupt is restored to the open status, let the CPU interrupt enable.
*2
*3
Are both IRQ FLAG1 and IRQ FLAG2 bits 0? N Y *2 IRQ FLAG0 = 0 Y IE on CPU side *3 Read CE register N
IE: Interrupt Enable
116
Semiconductor
[Basic check at the early stage of development] (a) Read/write check
MSM6542-010/2/03
Only the BANK 1/0 bit can be subject to read and write operations without a paritcular procedure. The interface can be checked by reading and writing the BANK 1/0 bit.
CF R - S1
(0, 0, 0, 0) (1, 1, 1, 1)
*1 *2
*1 *2
(D3, D2, D1, D0) Use addresses and data having values opposite to those in *1 above to charge or discharge the bus in the reverse phase. D3 is the BANK 1/0 bit. Same idea as *2
Read CF register Check D3 = 0 CF A - S1 (1, 0, 0, 0) (0, 1, 1, 1) *3
*3 *4
Read CF register Check D3 = 1
(b) Checking oscillation using software Oscillator operation can be checked using software through increment of clock registers, change of the IRQ FLAG1 and IRQ FLAG2 bits, 30-s adjustment, change of the read flag, and setting the DP bit at 0. These methods, except setting the DP bit at 0, affect the REST and STOP bits. Therefore, the method involved in the DP is used in the following flowcharts:
CF register BANK 1/0
*1, *2
1
CE' register DP 1 Read CE' register
*2 *1
The DP bit is not set at 1 for 62 s after it changes from 1 to 0. When the step marked *2 is executed within the 62s interval but oscillation is in progress, the loop marked *1 is completed within 62 s.
DP Y
1
N
1
117
MSM6542-01/02/03
Semiconductor
1
*2
CE' register DP 0
Time until the DP bit becomes 0 under assumption that oscillation is in progress. The time required for this loop is prolonged by the time equal to the one required to start oscillation. Usually, this time is 0.5 to 2 s.
*3
*2 *3
Idling for at least 11ms
Read CE' register
DP = 0 ? Y Oscillation is in progress
N
118
Semiconductor
Reference experimental data
MSM6542-010/2/03
XT
XT
CG VDD CG =12pF CD =32pF
CD
Crystral oscillator: P3 manufactured by Kinseki Co., Ltd. (32.768 kHz) Load capacity: CL=12pF Equivalent series resistance: 30k (MAX) Secondary temperature coefficient of frequency characteristics: -4.2 x 10-8 /C (MAX) Note: The temperature characteristics of the capacitors used are class 0.
o Dependency of oscillation frequency on power supply voltages /(PPM) 5 2 0 5 -5 6 3 4 VDD(V) Ta = 25C
o Dependency of IDD on power supply voltages (Ta = 25C) IDD(A) 20
10
o Dependency of oscillation frequency on temperatures -40 -20 0 20 40 60 80 Ta(C) VDD(V) 2 3 4 5 6
o Dependency of IDD on ambient temperatures
-50
IDD(A) 10 VDD = 2V
VDD = 5V
-100 / (PPM) o Dependency of oscillation frequencies on capacitance /(PPM) 40 20 0 5 -20 10 VDD = 2V CD = 32pF 15 20 CG (pF)
5 VDD = 3V VDD = 2V Ta (C) -40 -20 0 20 40 60 80
119
MSM6542-01/02/03 PACKAGE DIMENSIONS
18-pin plastic DIP
Semiconductor
(Unit: mm) 24.5 MAX 18 10
1 1-pin index mark area
9 7.62 0.30 0.3 MAX 2.54 MIN 5.1 MAX
6.7 MAX
0.65 MAX 2.54 0.25 0~ 15 Seating Plane
0.6 MAX
24-pin plastic DIP
32.3 MAX 24 10
(Unit: mm)
1 1-pin index mark area
9
14.2 MAX
15.24 0.30
0.3 MIN 5.1 MAX
0.65 MAX 2.54 0.25
2.54 MIN
0.6 MAX 0 ~ 15
Seating Plane
120
Semiconductor
20-pin plastic flat
MSM6542-010/2/03
(Unit: mm)
1.6 0.2 10.0 0.3 20 11 0 ~ 10
0 ~ 0.3 5.0 0.3 6.8 0.4
1
0.95 0.1
10 0.35 0.15
1-pin index mark area
24-pin plastic flat
(Unit: mm) 2.2 0.2 1.6 0.3 24 1.27 0.1 0.35 0.1 13 0 ~ 10
0.1 ~ 0.3
7.9 0.3
12.0 0.4
1 1-pin index mark area (gloss)
12
1.0 0.2
0.55 TYP
121

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